1. Field of the Invention
The present invention generally relates to synchronous memory devices and more specifically to reducing the latency needed to switch the speed of data transfers to and from the synchronous memory device.
2. Description of the Related Art
Conventional commercially available synchronous memory devices, such as DRAM (dynamic random access memory) or other clocked memory devices that use clocks or other signals to control the speed of their communication are at times configured to operate in a low speed mode in order to reduce the power consumed by a system including the synchronous memory device. The low speed mode is particularly useful as the number of portable, battery-powered devices has increased. In order to change speeds, a sequence of adjustments are made to prepare the synchronous memory device circuits to change the clock signal after which time the synchronous memory device resumes functioning at a lower clock speed. During the entry sequence, a phase-locked loop (PLL) or delay locked loop (DLL) that provides the internal clock signal is bypassed or the DLL is shut off altogether and the input clock that has changed frequency is provided to the memory core. The input clock at the changed frequency continues to be provided to the input of the PLL or DLL, causing the PLL or DLL output to become unlocked. Exiting the low speed mode requires a complimentary sequence of steps to enable the synchronous memory device to resume functioning at full speed. The internal clock bypass is removed, so that the PLL or DLL again provides the internal clock signal to the memory core. The input clock frequency is changed to full speed and the PLL/DLL requires many microseconds to lock to the changed input clock before data transactions can resume at a new frequency.
Although the entry and exit sequences may vary from one synchronous memory device manufacturer to another, each sequence includes time delays related to the PLL/DLL locking when the input clock to the synchronous memory device changes frequency. Because these delays are long relative to data transfer cycles, systems are configured to use the low speed mode only when the synchronous memory device will be accessed at the lower speed for a significant period of time. Therefore, the low speed mode is sometimes not used, resulting in higher power consumption.
Accordingly, what is needed in the art is a system and method for entering and exiting the low speed mode with lower latency. Lower latency for switching the synchronous memory device speed enables the low speed mode to be used more frequently and more effectively for shorter periods of time to reduce power consumption.